82598EB Datasheet, PDF (170/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Hardware EEPROM Sections
3.4.3.2.2.2 PCIe Analog Selector
Each part of the PCIe analog is reachable through a 2-byte bus (data/word). At the same time, access
must signal which part of the PCIe analog it targeted (SR0, SR1, … SC). To map this access, the
EEPROM uses a structure of one PCIe analog selector that indicates which internal target is accessed by
the next EEPROM word.
Bit
15:8
7:0
Name
Selector TAG = 0xFF
Target ID
Default
0xFF
0x0
Description
The 0xFF value in this EEPROM word identifies this word as a selector.
Identifies which internal PCIe analog target is accessed by the following
EEPROM word. Refer to the following table.
Target ID
00
01
02
03
04
05
06
07
08
09
SR Lane 0 Registers.
SR Lane 1 Registers.
SR Lane 2 Registers.
SR Lane 3 Registers.
SR Lane 4 Registers.
SR Lane 5 Registers.
SR Lane 6 Registers.
SR Lane 7 Registers.
SR registers of all lanes at the same time.
SC Register.
Target
3.4.3.2.2.3 PCIe Analog Word
Bit
15:8
7:0
Name
Add
Data
Default
0x0
0x0
Description
Register address in the PCIe ANA target.
The value to write in the register pointed to by the address.
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