82598EB Datasheet, PDF (371/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Field
Q_MAP[0]
Reserved
Q_MAP[1]
Reserved
Q_MAP[2]
Reserved
Q_MAP[3]
Reserved
Bit(s)
Initial
Value
Description
3:0
0x0
Defines the per-queue statistic register that is mapped to this queue.
7:4
0x0
Reserved
11:8
0x0
Defines the per-queue statistic register that is mapped to this queue.
15:12
0x0
Reserved
19:16
0x0
Defines the per-queue statistic register that is mapped to this queue.
23:20
0x0
Reserved
27:24
0x0
Defines the per-queue statistic register that is mapped to this queue.
31:28
0x0
Reserved
4.4.3.9.51 Queue Packets Received Count – QPRC (0x01030+ n*0x40[n=0..15];
R)
Field
QPRC
Bit(s)
Initial
Value
Description
31:0
0x0
Number of packets received for the queue.
4.4.3.9.52 Queue Packets Transmitted Count – QPTC (0x06030 +
n*0x40[n=0..15]; R)
Field
QPTC
Bit(s)
Initial
Value
Description
31:0
0x0
Number of packets transmitted for the queue.
4.4.3.9.53 Queue Bytes Received Count – QBRC (0x1034 + n*0x40[n=0..15]; R)
Field
QBRC
Bit(s)
Initial
Value
Description
31:0
0x0
Number of bytes received for the queue.
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