82598EB Datasheet, PDF (53/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Functional Description
3. Functional Description
3.1
Interconnects
3.1.1 PCIe
PCIe defines a set of requirements that address the majority of the targeted application classes.
Higher-end application requirements (Enterprise class servers and high-end communication platforms)
are addressed by advanced extensions.
To guarantee headroom for future applications of PCIe, a software-managed mechanism for introducing
capabilities is provided. Figure 3-1 shows the architecture.
Figure 3-1. PCIe Stack Structure
The PCIe physical layer consists of a differential transmit pair and a differential receive pair. Full-duplex
data on these two point-to-point connections is self-clocked such that no dedicated clock signals are
required. The bandwidth increases in direct proportion with frequency.
The packet is the fundamental unit of information exchange and the protocol includes message space to
replace the large amounts of side-band signals found on many buses. This movement of hard-wired
signals from the physical layer to messages within the transaction layer enables linear physical layer
width expansion for increased bandwidth.
53