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82598EB Datasheet, PDF (179/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet
Intel® 82598EB 10 GbE Controller - Hardware EEPROM Sections
3.4.3.4.2 EEPROM PCIe Configuration Space 0/1- Offset 1
Bit
15:10
9
8
7
6:5
4:0
Name
Default
Reserved
0x0
LAN Flash
1b
Disable
LAN Boot Disable 1b
Interrupt Pin
0b for
LAN0
1b for
LAN1
Reserved
MSI_X _N
00b
0x10
Description
Reserved.
A value of 1b disables the Flash logic. The Flash access BAR in the PCI
configuration space is also disabled.
A value of 1b disables the expansion ROM BAR in the PCI configuration space.
Controls the value advertised in the Interrupt Pin field of the PCI configuration
header for this device/function. A value of 0b, reflected in the Interrupt Pin,
field indicates that 82598 uses INTA#; a value of 1b indicates that 82598 uses
INTB#.
When one port is used, the configuration should be aligned to make sure INTA#
is used.
Reserved.
This field specifies the number of entries in the MSI-X tables for this function.
MSI_X_N is equal to the number of entries minus one. For example, a return
value of 0x7 means eight vectors are available. The 82598 supports a
maximum of 16 vectors.
The following table lists the different combinations for bits 9 and 8.
Bit 9
(Flash Disable)
0b
0b
1b
1b
Bit 8
(Boot Disable)
0b
1b
0b
1b
Functionality (Active Windows)
Flash and expansion ROM BARs are active.
Flash BAR is enabled and expansion ROM BAR is disabled.
Reserved
Flash and Expansion ROM BARs are disabled.
3.4.3.4.3 EEPROM PCIe Configuration Space 0/1 – Offset 2 Device ID
If the load vendor/device IDs in offset 0x7 of section PCIe General configuration is set, this word is read
in to initialize the device ID of the LAN function. The default value is 10B6.
3.4.3.5 EEPROM Core 0/1 Section
Word 0x9 points to the core configuration defaults of core 0 while word 0xA points to core 1 defaults.
Both sections are loaded at the de-assertion of their core master reset.
The structure of both sections is identical as listed in the following table:
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