82598EB Datasheet, PDF (78/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Table 3-11. Unique Fields
Device ID
Command,
Status
Latency Timer,
Cache Line Size
Memory BAR,
Flash BAR,
IO BAR,
Expansion ROM BAR
Interrupt Pin
The device ID reflected for each LAN device can be independently specified via an EEPROM.
Each LAN device implements its own Command/Status registers.
Each LAN device implements these registers uniquely. The system should program these
fields identically for each LAN to ensure consistent behavior and performance of each
device.
Each LAN device implements its own Base Address registers, enabling each device to claim
its own address region(s).
Each LAN device independently indicates which interrupt pin (INTA# or INTB#) is used by
that device’s MAC to signal system interrupts. The value for each LAN device can be
independently specified via an EEPROM, but only if both LAN devices are enabled.
3.1.1.14.3 Mandatory PCI Configuration Registers
The PCI configuration registers map is depicted below. Refer to the detailed descriptions for registers
loaded from the EEPROM at initialization. Initialization values of the configuration registers are marked
in parenthesis. Notation:
• Dotted – Fields are identical to all functions
• Light-blue – Read-only fields
• Magenta – Hardcoded
• Configuration registers are assigned one of the attributes listed in Table 3-12.
Table 3-12. Attributes of Configuration Registers
R/W
Description
RO
Read-only register. Register bits are read-only and cannot be altered by software.
RW
Read-write register. Register bits are read-write and can be either set or reset.
R/W1C
Read-only status, Write-1b-to-clear status register; writing a 0b to R/W1C bits has no effect.
ROS
Read-only register with sticky bits. Register bits are read-only and cannot be altered by software. Bits are not
cleared by reset and can only be reset with the PWRGOOD signal. Devices that consume AUX power are not allowed
to reset sticky bits when AUX power consumption (either via AUX power or PME Enable) is enabled.
RWS
Read-write register bits are read-write and can be either set or reset by software to the desired state. Bits are not
cleared by reset and can only be reset with the PWRGOOD signal. Devices that consume AUX power are not allowed
to reset sticky bits when AUX power consumption (either via AUX power or PME Enable) is enabled.
R/W1CS
Read-only status, Write-1b-to-clear status register. Register bits indicate status when read, a set bit, indicating a
status event, can be cleared by writing a 1b to it. Writing a 0b to R/W1C bits has no effect. Bits are not cleared by
reset and can only be reset with the PWRGOOD signal. Devices that consume AUX power are not allowed to reset
sticky bits when AUX power consumption (either via AUX power or PME Enable) is enabled.
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