82598EB Datasheet, PDF (466/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - LAN Fail-Over in LAN Teaming Mode
Table 5-15. Fail-Over Register
Bits
Field
0
RMP0EN
1
RMP1EN
2
MXP
3
PRPP
4
PRPPE
5
Reserved
6
RGAEN
8:7
Reserved
Bits
Field
9
TFOENODX
10:1
1
12:1
5
Reserved
GAC
Initial
Value
Read/
Write
Description
0x1
RO
RCV MNG port 0 Enable.
When this bit is set, it reports that management traffic will be received
from port 0.
0x1
RO
RCV MNG port 1 Enable.
When this bit is set, it reports that management traffic will be received
from port 1.
0x0
RO
MNG XMT Port.
0b - reports that management traffic should be transmitted through port
0.
1b – reports that MNG traffic should be transmitted through port 1.
0x0
RW
Preferred Primary Port.
0b – Port 0 is the preferred primary port.
1b – Port 1 is the preferred primary port.
0x0
RW
Preferred primary port enables.
0x0
RO
Reserved
0x0
Repeated Gratuitous ARP Enable.
If this bit is set, the 82598EB sends a configurable number of gratuitous
ARP packets (GAC bits of this register) using configurable interval (GATI
bits of this register) after the following events:
• System move to Dx.
• Fail-over event initiated 82598EB.
0x0
RO
Reserved
Initial
Value
Read/
Write
Description
0x0
RW
Teaming Fail-Over Enable on Dx.
Enable fail-over mechanism. Bits 3:8 are valid only if this bit is set.
0x0
RO
Reserved
0x0
RW
Gratuitous ARP Counter.
Indicates the number of gratuitous ARP that should be sent after a fail-
over event and after move to Dx.
The value of 0b means that there is no limit on the gratuitous ARP
packets to be sent.
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