82598EB Datasheet, PDF (171/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Hardware EEPROM Sections
3.4.3.3 EEPROM PCIe General Configuration Section
This section is loaded after a PCIe power good or PCIe in-band reset de-assertion. It contains general
configuration for the PCIe interface (not function specific) and is pointed to by word 0x06 in the
EEPROM (full-byte address; must be word aligned).
Offset
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
High Byte
Low Byte
Section Length = 0x0B
PCIe Init Configuration 1
PCIe Init Configuration 2
PCIe Init Configuration 3
PCIe Control Offset 4
PCIe Control Offset 5
PCIe Control Offset 6
PCIe Control Offset 7
PCIe Control Offset 8
PCIe Control Offset 9
PCIe Control Offset 10
PCIe Control Offset 11
Section
3.4.3.3.1
3.4.3.3.2
3.4.3.3.4
3.4.3.3.4
3.4.3.3.5
3.4.3.3.6
3.4.3.3.7
3.4.3.3.8
3.4.3.3.9
3.4.3.3.10
3.4.3.3.11
3.4.3.3.12
3.4.3.3.1 PCIe General Configuration – Section Length
The section length word contains the length of the section in words. Note that the sections length does
not contain the section length word itself.
3.4.3.3.2 PCIe Init Configuration 1 – Offset 1
Bit
15
Name
L0s Enable
Default
0b
Description
If the L0s Enable bit is set, the default value of the Active State Link PM
Control field in the PCIe Link Control Register is set to 01b (L0s entry
enabled).
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