82598EB Datasheet, PDF (6/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Contents
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.2.3 Legacy Receive Descriptor Format.................................................................... 219
3.5.2.4 Advanced Receive Descriptors ......................................................................... 221
3.5.2.5 Receive UDP Fragmentation Checksum ............................................................. 229
3.5.2.6 Receive Descriptor Fetching ............................................................................ 229
3.5.2.7 Receive Descriptor Write-Back......................................................................... 230
3.5.2.8 Receive Descriptor Queue Structure ................................................................. 230
3.5.2.9 Header Splitting and Replication ...................................................................... 232
3.5.2.10 Receive-Side Scaling (RSS) ............................................................................. 235
3.5.2.11 Receive Queuing for Virtual Machine Devices (VMDq).......................................... 240
3.5.2.12 Receive Checksum Offloading .......................................................................... 241
Transmit Functionality ................................................................................................... 244
3.5.3.1 Packet Transmission ...................................................................................... 244
3.5.3.2 Transmit Contexts ......................................................................................... 244
3.5.3.3 Transmit Descriptors ...................................................................................... 245
3.5.3.4 TCP Segmentation ......................................................................................... 256
3.5.3.5 IP/TCP/UDP Transmit Checksum Offloading in Non-Segmentation Mode ................ 270
3.5.3.6 Multiple Transmit Queues ............................................................................... 271
3.5.3.7 Transmit Completions Head Write Back............................................................. 272
Interrupts .................................................................................................................... 272
3.5.4.1 Registers ...................................................................................................... 272
3.5.4.2 Interrupt Moderation ...................................................................................... 274
3.5.4.3 Clearing Interrupt Causes ............................................................................... 276
3.5.4.4 Dynamic Interrupt Moderation ......................................................................... 276
3.5.4.5 TCP Timer Interrupt ....................................................................................... 277
3.5.4.6 MSI-X Interrupts ........................................................................................... 277
802.1q VLAN Support .................................................................................................... 278
3.5.5.1 802.1q VLAN Packet Format ............................................................................ 279
3.5.5.2 802.1q Tagged Frames ................................................................................... 279
3.5.5.3 Transmitting and Receiving 802.1q Packets ....................................................... 280
3.5.5.4 802.1q VLAN Packet Filtering .......................................................................... 280
DCA ............................................................................................................................ 281
3.5.6.1 Description ................................................................................................... 281
3.5.6.2 PCIe Message Format for DCA (MWr Mode) ....................................................... 283
LED's........................................................................................................................... 284
4. Programming Interface ........................................................................................................... 285
4.1 Address Regions ........................................................................................................................ 285
4.2 Memory-Mapped Access .............................................................................................................. 285
4.2.1 Memory-Mapped Access to Internal Registers and Memories ............................................... 285
4.2.2 Memory-Mapped Accesses to Flash .................................................................................. 285
4.2.3 Memory-Mapped Access to Expansion ROM....................................................................... 286
4.3 I/O-Mapped Access .................................................................................................................... 286
4.3.1 IOADDR (I/O Offset 0x00, RW) ....................................................................................... 286
4.3.2 IODATA (I/O Offset 0x04, RW)........................................................................................ 286
4.3.3 Undefined I/O Offsets .................................................................................................... 288
4.4 Device Registers ........................................................................................................................ 288
4.4.1 Terminology ................................................................................................................. 288
4.4.2 Register List ................................................................................................................. 288
4.4.3 Register Descriptions ..................................................................................................... 298
4.4.3.1 General Control Registers ............................................................................... 298
4.4.3.2 EEPROM/Flash Registers ................................................................................. 304
4.4.3.3 Interrupt Registers ........................................................................................ 312
4.4.3.4 Flow Control Registers Description ................................................................... 321
4.4.3.5 Receive DMA Registers ................................................................................... 324
4.4.3.6 Receive Registers .......................................................................................... 331
4.4.3.7 Transmit Register Descriptions ........................................................................ 344
4.4.3.8 Wake-Up Control Registers ............................................................................. 350
4.4.3.9 Statistic Registers .......................................................................................... 356
4.4.3.10 Management Filter Registers ........................................................................... 372
4.4.3.11 PCIe Registers............................................................................................... 382
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