82598EB Datasheet, PDF (415/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
To ensure software’s ability to read the same Link Partner Next Page (located across 2 registers), once
ANLPNP1 is read the ANLPNP2 register is locked until the ANLPNP2 register is read. ANLPNP2 does not
hold valid data before ANLPNP1 is read.
4.4.3.13.32Auto Negotiation Link Partner Next Page 2 Register – ANLPNP2
(0x042D8; RO)
Field
Reserved
LP AN Next Page
High
Bit(s)
31:16
15:0
Initial
Value
0x0
0x0
Description
Reserved
LP AN Next Page Fields D[47:32].
[15:0] = Unformatted Code.
To ensure software’s ability to read the same Link Partner Link Control Word (located across 2
registers), once ANLPNP1 is read the ANLPNP2 register is locked until the ANLPNP2 register is read.
ANLPNP2 does not hold valid data before ANLPNP1 is read.
4.4.3.13.33Core Analog Configuration Register - ATLASCTL (0x04800; RW)
Field
Reserved
Latch Address
Address
Data
Bit(s)
Initial
Value
Description
31:17
0b
Reserved
16
0b
0b = Normal write operation.
1b = Latch this address for next read transaction. The Data is ignored and is not
written on this transaction.
15:8
0b
Address to core analog registers
7:0
0b
Data to core Analog registers.
Data is ignored when bit 16 is set
Reading the core registers must be done using the following steps:
1. Send a write command with bit 16 set, and the desired reading offset in the Address field (bits
[15:8]).
2. Send a read command to the ATLASCTL. The returned data is from the indirect address in the core
register space which was provided in step (1).
To configure (write) registers in the core block the driver should write the proper address to the
ATLASCTL.Address and the data to be written to the ATLASCTL.Data.
§§
415