SH7014 Datasheet, PDF (98/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Exception Processing
5.3 Address Errors
5.3.1 Address Error Sources
Address errors occur when instructions are fetched or data read or written, as shown in table 5.5.
Table 5.5 Bus Cycles and Address Errors
Bus Cycle
Type
Bus
Master Bus Cycle Description
Address Errors
Instruction CPU
fetch
Instruction fetched from even address
Instruction fetched from odd address
None (normal)
Address error occurs
Instruction fetched from other than on-chip peripheral None (normal)
module space*
Instruction fetched from on-chip peripheral module
space*
Address error occurs
Instruction fetched from external memory space when Address error occurs
in single chip mode
Data
CPU or Word data accessed from even address
read/write DMAC _{Word data accessed from odd address}
None (normal)
Address error occurs
Longword data accessed from a longword boundary None (normal)
Longword data accessed from other than a long-word Address error occurs
boundary
Byte or word data accessed in on-chip peripheral
module space*
None (normal)
Longword data accessed in 16-bit on-chip peripheral None (normal)
module space*
Longword data accessed in 8-bit on-chip peripheral
module space*
Address error occurs
External memory space accessed in single-chip mode Address error occurs
Note: * See section 8, Bus State Controller.
Rev.5.00 Sep. 27, 2007 Page 64 of 716
REJ09B0398-0500