SH7014 Datasheet, PDF (133/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Cache Memory (CAC)
CK
Internal
address
Address
CSn
RD
Data
Mis-hit
Idle cycle
Idle cycle
Idle cycle
CS assert extension
Figure 7.5 Cache Fill Timing in Case of Non-Consecutive Cache Miss from Normal Space
(No Wait, No CS Assert Extension)
CK
Internal
address
Address
CSn
RD
Data
Miss-hit
CS assert additional extension
Figure 7.6 Cache Fill Timing in Case of Consecutive Cache Misses from Normal Space
(No Wait, CS Assert Extension)
Rev.5.00 Sep. 27, 2007 Page 99 of 716
REJ09B0398-0500