SH7014 Datasheet, PDF (158/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.3.2 Wait State Control
The number of wait states inserted into ordinary space access states can be controlled using the
WCR settings (figure 8.4). The specified number of Tw cycles are inserted as software wait cycles
at the timing shown in figure 8.4.
T₁
T_W
T₂
CK
Address
CSn
Read
RD
Data
Write
WRx
Data
Figure 8.4 Wait Timing of Ordinary Space Access (Software Wait Only)
When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 8.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when T_w state shifts to T₂ state.
Rev.5.00 Sep. 27, 2007 Page 124 of 716
REJ09B0398-0500