SH7014 Datasheet, PDF (295/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed
by a 0 write. For DMA controller activation, clearing can also be done automatically. Figure 10.47
shows the timing for status flag clearing by the CPU. Figure 10.48 shows timing for clearing due
to the DMA controller.
TSR write cycle
T₁
T₂
φ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 10.47 Timing of Status Flag Clearing by the CPU
DMAC
read cycle
T₁
T₂
DMAC
write cycle
T₁
T₂
φ
Address
Status flag
Source
address
Destination
address
Interrupt
request signal
Figure 10.48 Timing of Status Flag Clearing by DMAC Activation
Rev.5.00 Sep. 27, 2007 Page 261 of 716
REJ09B0398-0500