SH7014 Datasheet, PDF (131/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Cache Memory (CAC)
7.3.2 Cache Data Array Read/Write Space
The cache data array has a compulsory read/write (figure 7.4).
31
10 9
Address
Upper 22 bits of the data array space address
(22 bits)
21 0
Entry address
⎯
(8 bits)
(2 bits)
31
0
Data
Data
(32 bits)
Figure 7.4 Cache Data Array
Data Array Read: Designates entry address and reads out the corresponding line of data.
Data Array Write: Designates entry address and writes designated data to the corresponding line.
Rev.5.00 Sep. 27, 2007 Page 97 of 716
REJ09B0398-0500