SH7014 Datasheet, PDF (167/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.4.4 Burst Operation
High-Speed Page Mode: When the burst enable bit (BE) of the DCR is set, burst accesses can be
performed using high speed page mode. The timing is shown in figure 8.12. Wait cycles can be
inserted during burst accesses by using the DCR.
T_p
T_r
T_c1
T_c2
T_c1
T_c2
CK
Address
Row
Column
Column
Write
Data
RAS
CASx
RDWR
Read
Data
RAS
CASx
RDWR
Figure 8.12 DRAM Bus Cycle (High-Speed Page Mode)
RAS Down Mode: There are some instances where even if burst operation is selected, continuous
accesses to DRAM will not occur, but another space will be accessed instead part way through the
access. In such cases, if the RAS signal is maintained at low level during the time the other space
is accessed, it is possible to continue burst operation at the time the next DRAM same row address
is accessed. This is called RAS down mode.
To use RAS down mode, set both the BE and RASD bits of the DCR to 1.
Figures 8.13 and 8.14 show operation in RAS up and down modes.
Rev.5.00 Sep. 27, 2007 Page 133 of 716
REJ09B0398-0500