SH7014 Datasheet, PDF (336/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Watchdog Timer (WDT)
11.4 Usage Notes
11.4.1 TCNT Write and Increment Contention
If a timer counter increment clock pulse is generated during the T₃ state of a write cycle to the
TCNT, the write takes priority and the timer counter is not incremented (figure 11.8).
TCNT write cycle
T₁
T₂
T₃
CK
Address
TCNT address
Internal
write signal
TCNT
input clock
TCNT
N
M
Counter write data
Figure 11.8 Contention between TCNT Write and Increment
11.4.2 Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may
increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of bits CKS2 to CKS0.
11.4.3 Changing between Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
Rev.5.00 Sep. 27, 2007 Page 302 of 716
REJ09B0398-0500