SH7014 Datasheet, PDF (49/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Classification
Data bus
Bus control
Symbol
I/O
D0 to D15 I/O
CS0 to CS3 O
RD
O
WRH
O
WRL
O
WAIT
I
RAS
O
CASH
O
CASL
O
RDWR
O
AH
O
Multifunction TCLKA
I
Timer Pulse Unit _TCLKB
(MTU)
TCLKC
TCLKD
TIOC0A
I/O
TIOC0B
TIOC0C
TIOC0D
1. SH7014/16/17 Overview
Name
Function
Data bus
16-bit bidirectional data bus
Chip selects 0 to Chip select signals for external
3
memory or devices.
Read
Indicates reading from an external
device.
Upper write
Indicates writing the upper 8 bits of
external data.
Lower write
Indicates writing the lower 8 bits of
external data.
Wait
Input causes insertion of wait cycles
into the bus cycle during external
space access.
Row address
strobe
Timing signal for DRAM row address
strobe.
Upper column
address strobe
Timing signal for DRAM column
address strobe.
Output when the upper 8 bits of data
are accessed.
Lower column
address strobe
Timing signal for DRAM column
address strobe.
Output when the lower 8 bits of data
are accessed.
DRAM read/write DRAM write strobe signal.
Address hold
Address hold timing signal for
devices using an address/data
multiplex bus.
MTU timer clock Input pins for external clocks to the
input
MTU counter.
MTU input
capture/output
compare
(channel 0)
Channel 0 input capture input/output
compare output/PWM output pins.
Rev.5.00 Sep. 27, 2007 Page 15 of 716
REJ09B0398-0500