SH7014 Datasheet, PDF (118/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Interrupt Controller (INTC)
Bits 7 to 4, 1, 0⎯IRQ0 to IRQ3, IRQ6, IRQ7 Flags (IRQ0F to IRQ3F, IRQ6F, IRQ7F):
These bits display the IRQ0 to IRQ3, IRQ6, IRQ7 interrupt request status.
Bits 7 to 4, 1, 0
IRQ0F to IRQ3F,
IRQ6F, IRQ7F Detection Setting
0
Level detection
Edge detection
1
Level detection
Edge detection
Description
No IRQn interrupt request exists.
Clear conditions: When IRQn input is high level
No IRQn interrupt request was detected.
Clear conditions:
(initial value)
1. When a 0 is written after reading IRQnF = 1 status
2. When IRQn interrupt exception processing has been
executed
An IRQn interrupt request exists.
Set conditions: When IRQn input is low level
An IRQn interrupt request was detected.
Set conditions: When a falling edge occurs at an IRQn input
IRQ pin
Level
detection
Edge
detection
ISR.IRQnF
IRQnS
(0: level,
1: edge)
SQ
Selection
CPU
interrupt
request
RESIRQn
R
(IRQn interrupt acceptance/IRQnF = 0 write after IRQnF = 1 read)
Figure 6.2 External Interrupt Process
Rev.5.00 Sep. 27, 2007 Page 84 of 716
REJ09B0398-0500