SH7014 Datasheet, PDF (127/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Cache Memory (CAC)
7.1.3 Register Configuration
The cache has one register, which can be used to control the enabling or disabling of each cache
space. The register configuration is shown in table 7.1.
Table 7.1 Register Configuration
Name
Abbreviation R/W
Cache control register CCR
R/W
Note: * Bits 15 to 5 are undefined.
Initial
Value
H'0000*
Address
H'FFFF8740
Access Size
(Bits)
8, 16, 32
Rev.5.00 Sep. 27, 2007 Page 93 of 716
REJ09B0398-0500