SH7014 Datasheet, PDF (541/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Automatic SCI Bit Rate Adjustment
18. 128 kB Flash Memory (F-ZTAT)
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Low period (9 bits) measured (H'00 data)
High period
(1 or more bits)
Figure 18.10 Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the SH7017 measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The SH7017 calculates the bit rate
of the transmission from the host from the measured low period, and transmits one H'00 byte to
the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment
end indication (H'00) has been received normally, and transmit one H'55 byte to the SH7017. If
reception cannot be performed normally, initiate boot mode again (reset), and repeat the above
operations. Depending on the host's transmission bit rate and the SH7017's system clock
frequency, there will be a discrepancy between the bit rates of the host and the SH7017. To ensure
correct SCI operation, the host's transfer bit rate should be set to 4800bps, 9600bps.
Table 18.7 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of the SH7017 bit rate is possible. The boot program should be executed within this
system clock range.
Table 18.7 System Clock Frequencies for which Automatic Adjustment of SH7017 Bit Rate
is Possible
Host Bit Rate
9600bps
4800bps
System Clock Frequency for which Automatic Adjustment
of SH7017 Bit Rate is Possible
8 to 28.7MHz
4 to 20MHz
Rev.5.00 Sep. 27, 2007 Page 507 of 716
REJ09B0398-0500