SH7014 Datasheet, PDF (651/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
DMAC
DMA Channel Control Registers 0, 1
(CHCR0, CHCR1)
H'FFFF86CC (Channel 0)
H'FFFF86DC (Channel 1)
8/16/32
Item
Bit name
Initial value
R/W
Item
Bit name
Initial value
R/W
Item
Bit name
Initial value
R/W
Item
Bit name
Initial value
R/W
31
―
0
R
23
―
0
R
15
DM1
0
R/W
7
―
0
R
30
―
0
R
22
―
0
R
14
DM0
0
R/W
6
DS
0
R/W
29
―
0
R
21
―
0
R
13
SM1
0
R/W
5
TM
0
R/W
Bit
28
27
―
―
0
0
R
R
20
19
―
―
0
0
R
R
12
11
SM0
RS3
0
0
R/W
R/W
4
3
TS1
TS0
0
0
R/W
R/W
26
25
24
―
―
―
0
0
0
R
R
R
18
17
16
RL
AM
AL
0
0
0
R/W
R/W
R/W
10
9
8
RS2
RS1
RS0
0
0
0
R/W
R/W
R/W
2
1
0
IE
TE
DE
0
0
0
R/W
R/(W)
R/W
Bit
Name
18 Request Check Level (RL)
17 Acknowledge Mode (AM)
16 Acknowledge Level (AL)
15, 14 Destination Address Mode 1, 0
(DM1 and DM0)
Value
0
1
0
1
0
1
00
1
10
1
Description
Output DRAK with active high
(initial value)
Output DRAK with active low
Outputs DACK during read cycle
(initial value)
Outputs DACK during write cycle
Active high output
(initial value)
Active low output
Destination address fixed
(initial value)
Destination address incremented (+1 during 8-bit
transfer, +2 during 16-bit transfer, +4 during 32-bit
transfer)
Destination address decremented (–1 during 8-bit
transfer, –2 during 16-bit transfer, –4 during 32-bit
transfer)
(Setting prohibited)
Rev.5.00 Sep. 27, 2007 Page 617 of 716
REJ09B0398-0500