SH7014 Datasheet, PDF (679/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
WDT
Description
Overflow Interval*²
Bit
Name
Value
Clock Source
(φ = 28.7 MHz)
2 to 0 Clock Select 2 to 0
(CKS2 to CKS0)
0 0 0 φ/2
1 φ/64
(Initial value) 17.9 μs
573.4 μs
1 0 φ/128
1.1 ms
1 φ/256
2.3 ms
1 0 0 φ/512
4.6 ms
1 φ/1024
9.2 ms
1 0 φ/4096
36.7 ms
1 φ/8192
73.4 ms
Notes: 1. Section 11.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when
TCNT overflows in the watchdog timer mode.
2. The overflow interval listed is the time from when the TCNT begins counting at H'00 until an
overflow occurs.
Reset Control/Status Register (RSTCSR)
H'FFFF8612 (Write)
―
H'FFFF8613 (Read)
Bit
Item
7
6
5
4
3
2
1
0
Bit name WOVF
RSTE
―
―
―
―
―
―
Initial value
0
0
0
1
1
1
1
1
R/W
R/(W)*
R/W
R
R
R
R
R
R
Note: * Only 0 can be written in bit 7 to clear the flag.
Bit
Name
Value
Description
7
Watchdog Timer Overflow Flag
(WOVF)
0
No TCNT overflow in watchdog timer mode
(initial value)
Cleared when software reads WOVF, then writes 0 in
WOVF
1
Set by TCNT overflow in watchdog timer mode
6
Reset Enable (RSTE)
0
Not reset when TCNT overflows
(initial value)
LSI not reset internally, but TCNT and TCSR reset
within WDT.
1
Reset when TCNT overflows
Rev.5.00 Sep. 27, 2007 Page 645 of 716
REJ09B0398-0500