SH7014 Datasheet, PDF (262/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
TCNT value
H'FFFF
H'0000
CST bit
Time
TCFV
Figure 10.7 Free-Running Counter Operation
Periodic Counter Operation Example: Periodic counter operation is obtained for a given
channel's TCNT by selecting compare-match as a TCNT clear source. Set the TGR register for
period setting to output compare register and select counter clear upon compare-match using the
CCLR2 to CCLR0 bits of the timer control register (TCR). After these settings, the TCNT begins
incrementing as a periodic counter when the corresponding bit of TSTR is set to 1. When the
count matches the TGR register value, the TGF bit in the TSR is set to 1 and the counter is cleared
to H'0000. If the TGIE bit of the corresponding TIER is set to 1 at this point, the MTU will make
an interrupt request to the interrupt controller. After the compare-match, TCNT continues counting
from H'0000. Figure 10.8 shows an example of periodic counting.
TCNT value
TGR
Counter cleared by
TGR compare match
H'0000
CST bit
TGF
Time
Flag cleared by software
or DMAC activation
Figure 10.8 Periodic Counter Operation
Rev.5.00 Sep. 27, 2007 Page 228 of 716
REJ09B0398-0500