SH7014 Datasheet, PDF (426/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. High Speed A/D Converter ⎯ SH7014 ⎯
Table 13.7 A/D Conversion Times
CKS = 0
CKS = 1
Time
Symbol Min Typ Max
Min Typ Max
A/D conversion start
t
D
delay time
1.5 1.5 1.5
1.5
1.5
1.5
Input sampling time
t_SPL
20
20
20
40
40
40
A/D conversion time
t_CONV
42.5 42.5 42.5
82.5 82.5 82.5
Notes: 1. Unit: states
2. Table entries are for when PWR = 1. If 200 states have not elapsed since the ADST bit
has been set, no conversions are done until after those 200 states have occurred.
When PWR = 0, add 200 states to the first A/D conversion start delay time. When two
or more conversions are performed in succession, tcp is 20 cycles when CKS = 0, and
40 cycles when CKS = 1.
The CKS bit of the ADCSR is the operation time t_CONV, but set so that this is 2 μs or greater. Table
13.8 shows the operating frequency and CKS bit settings.
Table 13.8 Operating Frequency and CKS Bit Settings
Minimum Conversion Time (μs)
CKS Conversion Time (States) 28 MHz 20 MHz 16 MHz 10 MHz 8 MHz
0
42.5
⎯
2.1
2.6
4.3
5.3
1
82.5
2.9
4.2
5.0
8.3
10.3
Note: The indication "⎯" means the setting is not available.
Rev.5.00 Sep. 27, 2007 Page 392 of 716
REJ09B0398-0500