SH7014 Datasheet, PDF (269/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
10.4.4 Buffer Operation
Buffer operation is a function of channels 0, 3, and 4. TGRC and TGRD can be used as buffer
registers. Table 10.5 shows the register combinations for buffer operation.
Table 10.5 Register Combinations
Channel
0
General Register
TGR0A
TGR0B
Buffer Register
TGR0C
TGR0D
The buffer operation differs, depending on whether the TGR has been set as an input capture
register or an output compare register.
When TGR Is an Output Compare Register: When a compare-match occurs, the corresponding
channel buffer register value is transferred to the general register. Figure 10.16 shows an example.
Compare match signal
Buffer
register
General
register
Comparator
TCNT
Figure 10.16 Compare Match Buffer Operation
When TGR Is an Input Capture Register: When an input capture occurs, the timer counter
(TCNT) value is transferred to the general register (TGR), and the value that had been held up to
that time in the TGR is transferred to the buffer register (figure 10.17).
Input capture signal
Buffer
register
General
register
Figure 10.17 Input Capture Buffer Operation
TCNT
Rev.5.00 Sep. 27, 2007 Page 235 of 716
REJ09B0398-0500