SH7014 Datasheet, PDF (19/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
18.7.3 Erase Mode
Page
517
18.8.2 Software
525
Protection
18.11.4 Auto-Program 538
Mode
18.11.6 Status Read 543
Mode
Table 18.19 Status
Read Mode Return
Commands
22.3.3 Bus Timing 567
Table 22.7 Bus Timing
22.3.4 Direct Memory 579
Access Controller
Timing
Table 22.8 Direct
Memory Access
Controller Timing
Revision (See Manual for Details)
Description added
When erasing flash memory, the erase/erase-verify flowchart
shown in figure 18.14 should be followed.
To perform data or program erasure, set the 1 bit flash memory
area to be erased in erase block register 1 (EBR1) at least 10
µs after setting the SWE bit to 1 in flash memory control
register 1 (FLMCR1).
Description amended
Software protection can be implemented by setting the SWE bit
in FLMCR1, erase block register 1 (EBR1) and the RAMS bit in
the RAM emulation register (RAMER).
Description amended
3. The lower 8 bits of the transfer address must be H'00, H'80.
If a value other than an effective address is input,
processing will switch to a memory write operation but a
write error will be flagged.
4. Memory address transfer is performed in the second cycle
(figure 18.24). Do not perform transfer after the third cycle.
Note amended
Note: I/O2 and I/O3 are undefined at present.
Description amended and notes added
Conditions: V = 5.0 V ± 10%, AV = 5.0 V ±10%, AV = V
CC
CC
CC
CC
±10%, V_SS = AV_SS = 0 V, Ta = – 20 to +75°C
Notes: TPC is the set value of the TPC bit in DCR.
* The delay time Min values are reference values
(typ).)
Description amended
Conditions: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, AV_CC = V_CC
±10%, V = AV = 0 V, Ta = – 20 to +75°C
SS
SS
Rev.5.00 Sep. 27, 2007 Page xix of xxxiv
REJ09B0398-0500