SH7014 Datasheet, PDF (417/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. High Speed A/D Converter ⎯ SH7014 ⎯
13.4.5 Buffer Operation
When conversion ends on the relevant channel, the conversion result is stored in the ADDR, and
simultaneously, the previously stored result is transferred to another ADDR. Buffer operation can
be selected from the following:
• AN0 → ADDRA → ADDRB (Two-stage, one-group operation)
• AN0 → ADDRA → ADDRC, AN1 → ADDRB → ADDRD (Two-stage, two-group
operation)
• AN0 → ADDRA → ADDRB → ADDRC → ADDRD (Four-stage, one-group operation)
To use in combination with simultaneous sampling, set GRP = 1, BUFE1, BUFE0 = B'10 and
CH2 = 0. Buffer operation timing is shown in figure 13.7.
Rev.5.00 Sep. 27, 2007 Page 383 of 716
REJ09B0398-0500