SH7014 Datasheet, PDF (157/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.3 Accessing Ordinary Space
A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM
direct connections.
8.3.1 Basic Timing
Figure 8.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are
performed in 2 states.
T₁
T₂
CK
Address
Read
CSn
RD
Data
Write
WRx
Data
Figure 8.3 Basic Timing of Ordinary Space Access
During a read, irrespective of operand size, all bits in the data bus width for the access space
(address) are fetched by the LSI on RD, using the required byte locations.
During a write, the following signals are associated with transfer of these actual byte locations:
WRH (bits 15 to 8) and WRL (bits 7 to 0).
Rev.5.00 Sep. 27, 2007 Page 123 of 716
REJ09B0398-0500