SH7014 Datasheet, PDF (149/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
Bits 3 to 0⎯CS Space DMA Single Address Mode Access Wait Specification (DSW3, DSW2,
DSW1, DSW0): Specifies the number of waits for CS space access (0 to 15) during DMA single
address mode accesses. These bits are independent of the W bits of the WCR1.
Bit 3
DSW3
0
0
1
Bit 2
DSW2
0
0
⋅⋅⋅
1
Bit 1
DSW1
0
0
1
Bit 0
DSW0
0
1
1
Description
No wait (external wait input disabled)
1 wait (external wait input enabled)
15 wait (external wait input enabled)
(initial value)
8.2.5 DRAM Area Control Register (DCR)
DCR is a 16-bit read/write register that selects the number of waits, operation mode, number of
address multiplex shifts and the like for DRAM control.
After a power-on reset, write the initial values to the bits in DCR and do not change the values
afterward.
Do not perform any DRAM space accesses before DCR initial settings are completed.
DCR is initialized by power-on resets to H'0000, but is not initialized by software standbys.
Bit:
Initial value:
R/W:
15
TPC
0
R/W
14
RCD
0
R/W
13
TRAS1
0
R/W
12
TRAS0
0
R/W
11
DWW1
0
R/W
10
DWW0
0
R/W
9
DWR1
0
R/W
8
DWR0
0
R/W
Bit: 7
6
5
4
3
2
1
0
DIW
⎯
BE RASD ⎯
SZ0 AMX1 AMX0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R/W R/W
R
R/W R/W R/W
Bit 15⎯RAS Precharge Cycle Count (TPC): Specifies the minimum number of cycles after
RAS is negated before next assert.
Bit 15
TPC
0
1
Description
1.5 cycles
2.5 cycles
(initial value)
Rev.5.00 Sep. 27, 2007 Page 115 of 716
REJ09B0398-0500