SH7014 Datasheet, PDF (90/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Clock Pulse Generator (CPG)
External circuitry such as that shown in figure 4.5 is recommended around the PLL.
PLLCAP
PLLV_CC
PLLV_SS
R1: 3 kΩ
C1: 470 pF
Rp: 200 Ω
CPB: 0.1 μF*
V_CC
CB: 0.1 μF*
V_SS
Note: * CB and CPB are laminated ceramic capacitors
(Recommended values)
Figure 4.5 Cautions for Use of PLL Oscillator Circuit
Place oscillation stabilization capacitor C1 and resistor R1 near the PLL CAP pin, and ensure that
these lines do not cross any other signal lines. Supply the C1 ground from PLL V_SS.
Also, separate PLL V_CC and PLL V_SS, and the other V_CC and V_SS pins, from the board power supply
source, and be sure to insert bypass capacitors CPB and CB close to the pins.
4.2.2 External Clock Input Method
Figure 4.6 shows an example of an external clock input connection. In this case, make the external
clock high level to stop it when in standby mode. During operation, make the external input clock
frequency 4 to 10 MHz.
When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF.
Even when inputting an external clock, be sure to delay until after the oscillation stabilization time
(upon power-on) or after release from standby, in order to ensure the PLL stabilization time.
Rev.5.00 Sep. 27, 2007 Page 56 of 716
REJ09B0398-0500