SH7014 Datasheet, PDF (115/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Interrupt Controller (INTC)
6.3 Description of Registers
6.3.1 Interrupt Priority Registers A to H (IPRA to IPRH)
Interrupt priority registers A to H (IPRA to IPRH) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.
Correspondence between interrupt request sources and each of the IPRA to IPRH bits is shown in
table 6.4.
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 6.4 Interrupt Request Sources and IPRA to IPRH
Register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
15 to 12
IRQ0
Reserved
DMAC0
MTU0
MTU2
Reserved
A/D
WDT, BSC
Bits
11 to 8
7 to 4
IRQ1
IRQ2
Reserved IRQ6
DMAC1
Reserved
MTU0
MTU1
MTU2
Reserved
Reserved SCI0
Reserved CMT0
Reserved Reserved
3 to 0
IRQ3
IRQ7
Reserved
MTU1
Reserved
SCI1
CMT1
Reserved
Rev.5.00 Sep. 27, 2007 Page 81 of 716
REJ09B0398-0500