SH7014 Datasheet, PDF (552/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. 128 kB Flash Memory (F-ZTAT)
18.7.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the
ESU bit is cleared at least 10 μs later), the watchdog timer is cleared after the elapse of 10 μs or
more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1.
Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses
to be read. The dummy write should be executed after the elapse of 20 μs or more. When the flash
memory is read in this state (verify data is read in 32-bit units), the data at the latched address is
read. Wait at least 2 μs after the dummy write before performing this read operation. If the read
data has been erased (all “1”), a dummy write is performed to the next address, and erase-verify is
performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-
verify sequence in the same way. However, ensure that the erase/erase-verify sequence is not
repeated more than 60 times. When verification is completed, exit erase-verify mode, and wait for
at least 5 μs. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1.
If there are any unerased blocks, set 1 bit for the flash memory area to be erased, and repeat the
erase/erase-verify sequence in the same way.
Rev.5.00 Sep. 27, 2007 Page 518 of 716
REJ09B0398-0500