SH7014 Datasheet, PDF (330/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Watchdog Timer (WDT)
11.2.3 Reset Control/Status Register (RSTCSR)
Bit: 7
6
5
4
3
2
1
0
WOVF RSTE ⎯
⎯
⎯
⎯
⎯
⎯
Initial value: 0
0
0
1
1
1
1
1
R/W: R/(W)* R/W
R
R
R
R
R
R
Note: * Only 0 can be written in bit 7 to clear the flag.
The RSTCSR is an 8-bit readable and writable register. (The RSTCSR differs from other registers
in that it is more difficult to write. See section 11.2.4, Register Access, for details.) It controls
output of the internal reset signal generated by timer counter (TCNT) overflow. RSTCR is
initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal
reset signal generated by the overflow of the WDT. It is initialized to H'1F in standby mode.
Bit 7⎯Watchdog Timer Overflow Flag (WOVF): Indicates that the TCNT has overflowed
(H'FF to H'00) in the watchdog timer mode. It is not set in the interval timer mode.
Bit 7
WOVF
0
1
Description
No TCNT overflow in watchdog timer mode
(initial value)
Cleared when software reads WOVF, then writes 0 in WOVF
Set by TCNT overflow in watchdog timer mode
Bit 6⎯Reset Enable (RSTE): Selects whether to reset the chip internally if the TCNT overflows
in the watchdog timer mode.
Bit 6
RSTE
0
1
Description
Not reset when TCNT overflows
(initial value)
LSI not reset internally, but TCNT and TCSR reset within WDT.
Reset when TCNT overflows
Bit 5⎯Reserved: This bit always read as 0. The write value should always be 0.
Bits 4 to 0⎯Reserved: These bits always read as 1. The write value should always be 1.
Rev.5.00 Sep. 27, 2007 Page 296 of 716
REJ09B0398-0500