SH7014 Datasheet, PDF (100/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Exception Processing
5.4.2 Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously
(overlap), the interrupt controller (INTC) determines their relative priorities and starts up
processing according to the results.
The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest
and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is
always accepted. IRQ interrupts and on-chip peripheral module interrupt priority levels can be set
freely using the INTC's interrupt priority level setting registers A through H (IPRA to IPRH) as
shown in table 5.7. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See
section 6.3.1, Interrupt Priority Registers A to H (IPRA to IPRH), for more information on IPRA
to IPRH.
Table 5.7 Interrupt Priority Order
Type
NMI
IRQ
Priority Level
16
0 to 15
On-chip peripheral module 0 to 15
Comment
Fixed priority level. Cannot be masked.
Set with interrupt priority level setting registers A
through H (IPRA to IPRH).
Set with interrupt priority level setting registers A
through H (IPRA to IPRH).
5.4.3 Interrupt Exception Processing
When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI
is always accepted, but other interrupts are only accepted if they have a priority level higher than
the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, exception processing begins. In interrupt exception processing, the
CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted
interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set
in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from
the exception processing vector table for the accepted interrupt, that address is jumped to and
execution begins. See section 6.4, Interrupt Operation, for more information on the interrupt
exception processing.
Rev.5.00 Sep. 27, 2007 Page 66 of 716
REJ09B0398-0500