SH7014 Datasheet, PDF (521/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. I/O Ports (I/O)
17.7.2 Port F Data Register (PFDR)
Bit: 7
6
5
4
3
2
1
0
PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR
Initial value: *
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
Note: * Initial values are dependent on the status of the pins at the time of the reads.
PFDR is an 8-bit read-only register that stores data for port F. The bits PF7DR to PF0DR
correspond to the PF7/AN7 to PF0/AN0 pins. Any value written into these bits is ignored, and
there is no effect on the status of the pins. When any of the bits are read, the pin status rather than
the bit value is read directly. However, when an A/D converter analog input is being sampled,
values of 1 are read out. Table 17.17 shows the read/write operations of the port F data register.
PFDR is not initialized by power-on resets, standby mode, or sleep mode (the bits always reflect
the pin status).
Table 17.17 Read/Write Operation of the Port F Data Register (PFDR)
Pin I/O Pin Function
Input
Ordinary
ANn: analog input
Note: n = 7 to 0
Read
Pin status is read
1 is read
Write
Ignored (no effect on pin status)
Ignored (no effect on pin status)
Rev.5.00 Sep. 27, 2007 Page 487 of 716
REJ09B0398-0500