SH7014 Datasheet, PDF (14/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
12.5.7 Constraints on 366
DMAC Use
13.1.1 Features
367
13.4 Operation
378
13.4.7 Conversion 388
Start Modes
Revision (See Manual for Details)
Description amended
• When using an external clock source for the synchronization
clock, update the TDR with the DMAC , and then after
five system clocks or more elapse, input a transmit clock. If
a transmit clock is input in the first four system clocks after
the TDR is written, an error may occur (figure 12.22).
Description amended
• High-speed conversion
⎯ Minimum conversion time:
2.9 µs per channel (for 28-MHz operation)
1.4 μs per channel during continuous conversion
Description amended
• In buffer operation, the previous conversion result is saved
in a buffer register at the end of a conversion for the
relevant channel.
• In simultaneous sampling operation, the analog input
voltages of two channels are sampled simultaneously then
converted in order.
• Software, a timer conversion start trigger (MTU) can be
selected as the conversion start condition.
Description amended
In the low-power conversion mode, power is applied to the
analog circuitry simultaneous to the conversion start (ADST
set). When 200 cycles of the reference clock have elapsed,
conversion becomes possible for the analog circuit and the first
A/D conversion begins. When performing consecutive
conversions, the second and later conversions are executed in
20 cycles. Select the basic clock with the CKS bit of the
ADCSR. When the A/D conversion ends, ADST is cleared to 0
and the analog circuit power supply is automatically cut off.
Because the analog circuit is only active during the A/D
conversion operation period in this mode, current consumption
can be reduced.
Rev.5.00 Sep. 27, 2007 Page xiv of xxxiv
REJ09B0398-0500