SH7014 Datasheet, PDF (653/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
DMAC
Bit
Name
1
Transfer End Flag (TE)
0
DMAC Enable (DE)
Value
0
1
0
1
Description
DMATCR—specified transfer count not ended
(initial value)
Clear condition: 0 write after TE = 1 read,
Power-on reset, standby mode
DMATCR specified number of transfers
completed
Operation of the corresponding channel
disabled
(initial value)
Operation of the corresponding channel
enabled
DMAC Operation Register (DMAOR)
Item
15
14
13
Bit name
―
―
―
Initial value
0
0
0
R/W
R
R
R
Item
7
6
5
Bit name
―
―
―
Initial value
0
0
0
R/W
R
R
R
Note: * 0 write only is valid after 1 is read.
H'FFFF86B0
Bit
12
11
―
―
0
0
R
R
4
3
―
―
0
0
R
R
10
―
0
R
2
AE
0
R/(W)
8/16/32
9
―
0
R
1
NMIF
0
R/(W)*
8
―
0
R
0
DME
0
R/W*
Bit
Name
2
Address Error Flag (AE)
1
NMI Flag (NMIF)
0
DMAC Master Enable (DME)
Value
0
1
0
1
0
1
Description
No address error, DMA transfer enabled (initial value)
Clearing condition: Write AE = 0 after reading AE = 1
Address error, DMA transfer disabled
Setting condition: Address error due to DMAC
No NMI interrupt, DMA transfer enabled (initial value)
Clearing condition: Write NMIF = 0 after reading NMIF
=1
NMI has occurred, DMC transfer prohibited
Set condition: NMI interrupt occurrence
Disable operation on all channels
(initial value)
Enable operation on all channels
Rev.5.00 Sep. 27, 2007 Page 619 of 716
REJ09B0398-0500