SH7014 Datasheet, PDF(198/754 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

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SH7014 Datasheet, PDF (198/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

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9. Direct Memory Access Controller (DMAC)

On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer

request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 9.4,

there are eight transfer request signals: three from the multifunction timer pulse unit (MTU),

which are compare match or input capture interrupts; the receive data full interrupts (RxI) and

transmit data empty interrupts (TxI) of the two serial communication interfaces (SCI); and the A/D

conversion end interrupt (ADI) of the A/D converter. When DMA transfers are enabled (DE = 1,

DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request

signal.

The transfer request source need not be the data transfer source or transfer destination. However,

when the transfer request is set by RxI (transfer request because SCI's receive data is full), the

transfer source must be the SCI's receive data register (RDR). When the transfer request is set by

TxI (transfer request because SCI's transmit data is empty), the transfer destination must be the

SCI's transmit data register (TDR). Also, if the transfer request is set to the A/D converter, the data

transfer destination must be the A/D converter register.

Table 9.4 Selecting On-Chip Peripheral Module Request Modes with the RS Bits

DMAC Transfer

RS3 RS2 RS1 RS0 Request Source

DMA Transfer

Destin-

Request Signal Source ation Bus Mode

0110

1

1000

MTU*2

MTU*2

MTU*2

TGI0A

TGI1A

TGI2A

Any*1

Any*1

Any*1

Any*1

Any*1

Any*1

Burst/cycle steal

Burst/cycle steal

Burst/cycle steal

1 Prohibited

1 0 Prohibited

1

100

1

A/D

SCI0*3 transmit block

SCI0*3 receive block

ADI

TxI0

RxI0

ADDR*4 Any*1

Any*1 TDR0

RDR0 Any*1

Burst/cycle steal

Burst/cycle steal

Burst/cycle steal

10

1

SCI1*3 transmit block TxI1

SCI1*3 receive block RxI1

Any*1 TDR1

RDR1 Any*1

Burst/cycle steal

Burst/cycle steal

Notes: 1. External memory, memory-mapped external device, on-chip memory, on-chip

peripheral module (excluding DMAC, BSC).

2. MTU: Multifunction timer pulse unit.

3. SCI0, SCI1: Serial communications interface.

4. ADDR: A/D converter's A/D register.

In order to output a transfer request from an on-chip peripheral module, set the relevant interrupt

enable bit for each module, and output an interrupt signal.

Rev.5.00 Sep. 27, 2007 Page 164 of 716

REJ09B0398-0500

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