SH7014 Datasheet, PDF (225/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
Section 10 Multifunction Timer Pulse Unit (MTU)
10.1 Overview
The SuperH microcomputer has an on-chip 16-bit multifunction timer pulse unit (MTU) with three
channels of 16-bit timers.
10.1.1 Features
• Can process a maximum of eight different pulse outputs and inputs.
• Has eight timer general registers (TGR): four for channel 0, and two each for channels 1 and 2
that can be set to function independently as output compare or input capture. The channel 0
TGRC and TGRD registers can be used as buffer registers.
• Can select eight counter input clock sources for all channels
• All channels can be set for the following operating modes:
⎯ Compare match waveform output: 0 output/1 output/toggle output selectable.
⎯ Input capture function: Selectable rising edge, falling edge, or both rising and falling edge
detection.
⎯ Counter clearing function: Counters can be cleared by a compare-match or input capture.
⎯ Synchronizing mode: Two or more timer counters (TCNT) can be written to
simultaneously. Two or more timer counters can be simultaneously cleared by a compare-
match or input capture. Counter synchronization functions enable synchronized register
input/output.
⎯ PWM mode: PWM output can be provided with any duty cycle. When combined with the
counter synchronizing function, up to seven-phase PWM output is enabled (with channels
0 to 2 set to PWM mode 2 and channel 0 synchronized with the TGR0A register (channels
0 to 2 phase output: 3, 2, 2)).
• Channels 0 can be set for buffer operation
⎯ Input capture register double buffer configuration possible
⎯ Output compare register automatic re-write possible
• Channels 1, 2 can be independently set to the phase counting mode
⎯ Two-phase encoder pulse up/down count possible
• Cascade connection operation
⎯ Can be operated as a 32-bit counter by using the channel 2 input clock for channel 1
overflow/underflow
• High speed access via internal 16-bit bus
Rev.5.00 Sep. 27, 2007 Page 191 of 716
REJ09B0398-0500