SH7014 Datasheet, PDF (682/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
SCI
Serial Control Register (SCR)
H'FFFF81A2 (Channel 0)
8/16
H'FFFF81B2 (Channel 1)
Item
Bit name
Initial value
R/W
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
Bit
4
3
RE
MPIE
0
0
R/W
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
0
R/W
Bit
Name
Value
Description
7
Transmit Interrupt Enable
(TIE)
0
Transmit-data-empty interrupt request (TXI) is disabled *¹
(initial value)
1
Transmit-data-empty interrupt request (TXI) is enabled
6
Receive Interrupt Enable
(RIE)
0
Receive-data-full interrupt (RXI) and receive-error interrupt
(ERI) requests are disabled*²
(initial value)
1
Receive-data-full interrupt (RXI) and receive-error interrupt
(ERI) requests are enabled
5
Transmit Enable (TE)
0
Transmitter disabled*³
(initial value)
1
Transmitter enabled*⁴
4
Receive Enable (RE)
0
Receiver disabled*⁵
(initial value)
1
Receiver enabled*⁶
3
Multiprocessor Interrupt
Enable (MPIE)
0
Multiprocessor interrupts are disabled
(normal receive operation)
(initial value)
MPIE is cleared when the MPIE bit is cleared to 0, or the
multiprocessor bit (MPB) is set to 1 in receive data.
1
Multiprocessor interrupts are enabled*⁷
Receive-data-full interrupt requests (RXI), receive-error
interrupt requests (ERI), and setting of the RDRF, FER, and
ORER status flags in the serial status register (SSR) are
disabled until data with the multiprocessor bit set to 1 is
received.
2
Transmit-End Interrupt
Enable (TEIE)
0
Transmit-end interrupt (TEI) requests are disabled*⁸
(initial value)
1
Transmit-end interrupt (TEI) requests are enabled*⁸
Rev.5.00 Sep. 27, 2007 Page 648 of 716
REJ09B0398-0500