SH7014 Datasheet, PDF (22/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4.2.2 External Clock Input Method............................................................................... 56
4.3 Prescaler............................................................................................................................ 57
Section 5 Exception Processing....................................................................................... 59
5.1 Overview........................................................................................................................... 59
5.1.1 Types of Exception Processing and Priority ........................................................ 59
5.1.2 Exception Processing Operations......................................................................... 60
5.1.3 Exception Processing Vector Table ..................................................................... 61
5.2 Resets ................................................................................................................................ 63
5.2.1 Power-on Reset .................................................................................................... 63
5.3 Address Errors .................................................................................................................. 64
5.3.1 Address Error Sources ......................................................................................... 64
5.3.2 Address Error Exception Processing.................................................................... 65
5.4 Interrupts........................................................................................................................... 65
5.4.1 Interrupt Sources.................................................................................................. 65
5.4.2 Interrupt Priority Level ........................................................................................ 66
5.4.3 Interrupt Exception Processing ............................................................................ 66
5.5 Exceptions Triggered by Instructions ............................................................................... 67
5.5.1 Types of Exceptions Triggered by Instructions ................................................... 67
5.5.2 Trap Instructions .................................................................................................. 67
5.5.3 Illegal Slot Instructions ........................................................................................ 68
5.5.4 General Illegal Instructions.................................................................................. 68
5.6 When Exception Sources Are Not Accepted .................................................................... 69
5.6.1 Immediately after a Delayed Branch Instruction ................................................. 69
5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 69
5.7 Stack Status after Exception Processing Ends .................................................................. 70
5.8 Usage Notes ...................................................................................................................... 71
5.8.1 Value of Stack Pointer (SP) ................................................................................. 71
5.8.2 Value of Vector Base Register (VBR) ................................................................. 71
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 71
Section 6 Interrupt Controller (INTC)........................................................................... 73
6.1 Overview........................................................................................................................... 73
6.1.1 Features................................................................................................................ 73
6.1.2 Block Diagram..................................................................................................... 73
6.1.3 Pin Configuration................................................................................................. 75
6.1.4 Register Configuration......................................................................................... 75
6.2 Interrupt Sources............................................................................................................... 76
6.2.1 NMI Interrupts ..................................................................................................... 76
6.2.2 IRQ Interrupts ...................................................................................................... 76
Rev.5.00 Sep. 27, 2007 Page xxii of xxxiv
REJ09B0398-0500