SH7014 Datasheet, PDF (173/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.5.3 CS Assertion Extension
The timing diagram when CS assertion extension is set for address/data multiplexed I/O space
access is shown in figure 8.19.
T_a1
T_a2
T_a3
T_a4
T_h
T₁
T₂
T_f
Address
CS3
AH
Read
RD
Data
Write
WRx
Data
Address output
Address output
Data input
Data output
Figure 8.19 Wait Timing for Address/Data Multiplexed I/O Space
When CS Assertion Extension is Set
Rev.5.00 Sep. 27, 2007 Page 139 of 716
REJ09B0398-0500