SH7014 Datasheet, PDF (284/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
and the TGR0B and TGR0D registers are employed for buffer operation. The channel 1 counter
input clock is used as the TGR0B register input capture source, and a pulse width of four times the
2-phase encoder pulse is detected.
The channel 1 TGR1A and TGR1B registers are set for the input capture function, the channel 0
TGR0A and TGR0C register compare-match is used as an input capture source, and all of the
control period increment and decrement values are stored. This procedure enables the accurate
detection of position and speed.
TCLKA
TCLKB
Edge
detection
circuit
Channel 1
TCNT1
TGR1A (speed
period capture)
TGR1B (position
period capture)
TCNT0
TGR0A (speed
+
control period)
−
TGR0C (position
+
control period)
−
TGR0B (pulse
width capture)
TGR0D (buffer
operation)
Channel 0
Figure 10.33 Phase Count Mode Application Example
Rev.5.00 Sep. 27, 2007 Page 250 of 716
REJ09B0398-0500