SH7014 Datasheet, PDF (74/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Instruction
DMULS.L Rm,Rn
Instruction Code
0011nnnnmmmm1101
DMULU.L Rm,Rn
0011nnnnmmmm0101
DT
Rn
0100nnnn00010000
EXTS.B Rm,Rn
0110nnnnmmmm1110
EXTS.W Rm,Rn
0110nnnnmmmm1111
EXTU.B Rm,Rn
0110nnnnmmmm1100
EXTU.W Rm,Rn
0110nnnnmmmm1101
MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
MUL.L Rm,Rn
MULS.W Rm,Rn
0000nnnnmmmm0111
0010nnnnmmmm1111
MULU.W Rm,Rn
0010nnnnmmmm1110
NEG
NEGC
Rm,Rn
Rm,Rn
0110nnnnmmmm1011
0110nnnnmmmm1010
Operation
Exec.
Cycles T Bit
Signed operation of 2 to 4* ⎯
Rn × Rm → MACH,
MACL 32 × 32 → 64 bit
Unsigned operation of 2 to 4* ⎯
Rn × Rm → MACH,
MACL 32 × 32 → 64 bit
Rn − 1 → Rn, when 1
Rn is 0, 1 → T. When
Rn is nonzero, 0 → T
Comparison
result
A byte in Rm is sign- 1
⎯
extended → Rn
A word in Rm is sign- 1
⎯
extended → Rn
A byte in Rm is zero- 1
⎯
extended → Rn
A word in Rm is zero- 1
⎯
extended → Rn
Signed operation of 3/
⎯
(Rn) × (Rm) + MAC → (2 to 4)*
MAC 32 × 32 → 64 bit
Signed operation of 3/(2)* ⎯
(Rn) × (Rm) + MAC →
MAC 16 × 16 + 64 →
64 bit
Rn × Rm → MACL,
32 × 32 → 32 bit
2 to 4* ⎯
Signed operation of
Rn × Rm → MAC
16 × 16 → 32 bit
1 to 3* ⎯
Unsigned operation of 1 to 3* ⎯
Rn × Rm → MAC
16 × 16 → 32 bit
0 − Rm → Rn
1
⎯
0 − Rm − T → Rn,
1
Borrow → T
Borrow
Rev.5.00 Sep. 27, 2007 Page 40 of 716
REJ09B0398-0500