SH7014 Datasheet, PDF (203/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CK
A21 to A0
CSn
D15 to D0
RD
WRH, WRL
DACK
9. Direct Memory Access Controller (DMAC)
Transfer source
address
Transfer destination
address
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Note: Transfer between external memories with DACK are output during read
cycle.
Figure 9.6 Example of Transfer Timing in Dual Address Mode
Rev.5.00 Sep. 27, 2007 Page 169 of 716
REJ09B0398-0500