SH7014 Datasheet, PDF (37/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1. SH7014/16/17 Overview
• DRAM burst access function
⎯ Supports high-speed access mode for DRAM
• DRAM refresh function
⎯ Programmable refresh interval
⎯ Supports CAS-before-RAS refresh and self-refresh modes
• Wait cycles can be inserted using an external WAIT signal
• Address data multiplex I/O devices can be accessed
Note: No bus release
Direct Memory Access Controller (DMAC) (2 Channels):
• Supports cycle-steal and burst transfers
• Supports single address mode and dual address mode transfers
• Priority order: fixed at channel 0 > channel 1
• Transfer counter: 16 bits
• Transfer request sources: external DREQ input, auto-request, and on-chip supporting modules
• Address space: 4 Gbytes
• Choice of 8-, 16-, or 32-bit transfer data size
Multifunction Timer/Pulse Unit (MTU) (3 Channels):
• Maximum 8 types of waveform output or maximum 16 types of pulse I/O processing possible
based on 16-bit timer, 3 channels
• 8 dual-use output compare/input capture registers
• 8 independent comparators
• 8 types of counter input clock
• Input capture function
• Pulse output mode
⎯ One shot, toggle, PWM
• Phase calculation mode
⎯ 2-phase encoder calculation processing
Compare Match Timer (CMT) (Two Channels):
• 16-bit free-running counter
• One compare register
• Generates an interrupt request upon compare match
Rev.5.00 Sep. 27, 2007 Page 3 of 716
REJ09B0398-0500