SH7014 Datasheet, PDF (61/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Addressing
Mode
Instruction
Format
Effective Addresses Calculation
Indirect register
addressing with
displacement
@(disp:4, The effective address is Rn plus a 4-bit
Rn)
displacement (disp). The value of disp is zero-
extended, and remains the same for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
Rn
disp
(zero-extended)
+
×
Rn + disp × 1/2/4
Equation
Byte: Rn +
disp
Word: Rn +
disp × 2
Longword:
Rn + disp × 4
1/2/4
Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0.
register
addressing
Rn
+
Rn + R0
Rn + R0
R0
Indirect GBR
addressing with
displacement
@(disp:8, The effective address is the GBR value plus an
GBR)
8-bit displacement (disp). The value of disp is zero-
extended, and remains the same for a byte opera-
tion, is doubled for a word operation, and is
quadrupled for a longword operation.
GBR
disp
+
(zero-extended)
×
GBR
+ disp × 1/2/4
Byte: GBR +
disp
Word: GBR +
disp × 2
Longword:
GBR + disp ×
4
1/2/4
Rev.5.00 Sep. 27, 2007 Page 27 of 716
REJ09B0398-0500