SH7014 Datasheet, PDF (286/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
Table 10.13 MTU Interrupt Sources
Interrupt
Channel Source Description
DMAC
Activation
Priority*
0
TGI0A
TGR0A input capture/compare-match Yes
High
TGI0B
TGR0B input capture/compare-match No
TGI0C
TGR0C input capture/compare-match No
TGI0D
TGR0D input capture/compare-match No
TCI0V
TCNT0 overflow
No
1
TGI1A
TGR1A input capture/compare-match Yes
TGI1B
TGR1B input capture/compare-match No
TCI1V
TCNT1 overflow
No
TCI1U
TCNT1 underflow
No
2
TGI2A
TGR2A input capture/compare-match Yes
TGI2B
TGR2B input capture/compare-match No
TCI2V
TCNT2 overflow
No
TCI2U
TCNT2 underflow
No
Low
Note: * Indicates the initial status following reset. The ranking of channels can be altered using
the interrupt controller.
10.5.2 DMAC Activation
The TGRA register input capture/compare-match interrupt of any channel can be used as a source
to activate the on-chip DMAC. For details, refer to section 9, Direct Memory Access Controller
(DMAC).
The MTU has three TGRA register input capture/compare-match interrupts, one for any channel,
that can be used as DMAC activation sources.
10.5.3 A/D Converter Activation
The TGRA register input capture/compare-match of any channel can be used to activate the on-
chip A/D converter.
If the TTGE bit of the TIER is already set to 1 when the TGFA flag in the TSR is set to 1 by a
TGRA register input capture/compare-match of any of the channels, an A/D conversion start
request is sent to the A/D converter. If the MTU conversion start trigger is selected at such a time
on the A/D converter side when this happens, the A/D conversion starts.
Rev.5.00 Sep. 27, 2007 Page 252 of 716
REJ09B0398-0500