SH7014 Datasheet, PDF (302/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
10.7.8 Contention between Buffer Register Write and Input Capture
If an input capture signal is issued in the T₂ state of the buffer write cycle, write to the buffer
register does not occur, and buffer operation takes priority (figure 10.55).
φ
Address
Write signal
Input capture
signal
TCNT
Buffer register write cycle
T₁
T₂
Buffer register
address
N
TGR
M
N
Buffer
register
M
Figure 10.55 Buffer Register Write and Input Capture Contention
Rev.5.00 Sep. 27, 2007 Page 268 of 716
REJ09B0398-0500