SH7014 Datasheet, PDF (420/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. High Speed A/D Converter ⎯ SH7014 ⎯
Table 13.5 Conversion Channel and ADF Flag Setting/Clearing Conditions During Buffer
Operation 2
Channel Setting
Sampling Channel
CH2 CH1 CH0 BUFE1, BUFE0 = B'01 BUFE1, BUFE0 = B'10 BUFE1, BUFE0 = B'11
00⎯
*
*
*
10
AN0, AN2 (ADDRC)
1
AN0, AN2, AN3
(ADDRD)
100
AN0, AN2 to AN4
(ADDRE)
AN0, AN1, AN4
(ADDRE)
AN0, AN4 (ADDRE)
1
AN0, AN2 to AN5
AN0, AN1, AN4, AN5 AN0, AN4, AN5
(ADDRF)
(ADDRF)
(ADDRF)
10
AN0, AN2 to AN6
(ADDRG)
AN0, AN1, AN4 to AN6 AN0, AN4 to AN6
(ADDRG)
(ADDRG)
1
AN0, AN2 to AN7
AN0, AN1, AN4 to AN7 AN0, AN4 to AN7
(ADDRH)
(ADDRH)
(ADDRH)
Note: * See table 13.4.
ADF Flag Clearing: When the DMAC is started up due to an A/D conversion end interrupt, the
ADF flag is cleared when the ADDR specified in table 13.4 or 13.5 has been read.
Resetting the Number of Buffer Operations: Clear the BUFE1 and BUFE0 bits to B'00 in
conversion standby mode or when the converter has been halted. The number of buffer operations
is cleared to 0.
Updating Buffer Operations: Clear the BUFE1 and BUFE0 bits to B'00 in conversion standby
mode or when the converter has been halted. Thereafter, set BUFE1 and BUFE0, and the buffer
operations shown in table 13.4 and 13.5 are performed when conversion is resumed.
13.4.6 Simultaneous Sampling Operation
With simultaneous sampling, continuous conversion is conducted with sampling of the input
voltages on two channels at the same time. Simultaneous sampling is valid in group mode.
Channels for sampling are determined by the CH2 and CH1 bits of the RDSCR. The combinations
are shown in table 13.6. For example, if GRP = 1 when CH2 and CH1 = B'11, sampling occurs in
order in the following pairs: AN0, AN1→AN2, AN3→AN4, AN5→AN6, AN7. Sampling timing
is shown in figure 13.9.
Rev.5.00 Sep. 27, 2007 Page 386 of 716
REJ09B0398-0500